138 lines
10 KiB
BibTeX
138 lines
10 KiB
BibTeX
@article{schneier_modeling_1999,
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title = {Modeling {Security} {Threats}},
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url = {https://www.schneier.com/academic/archives/1999/12/attack_trees.html},
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author = {Schneier, Bruce},
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year = {1999},
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journal = {Dr. Dobb's Journal},
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note = {vol. 24, no.12}
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}
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@article{phillips_graph-based_1998,
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title = {A graph-based system for network-vulnerability analysis},
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volume = {Part F1292},
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issn = {1581131682},
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doi = {10.1145/310889.310919},
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abstract = {This paper presents a graph-based approach to network vulnerability analysis. The method is flexible, allowing analysis of attacks from both outside and inside the network. It can analyze risks to a specific network asset, or examine the universe of possible consequences following a successful attack. The graph-based tool can identify the set of attack paths that have a high probability of success (or a low "effort" cost) for the attacker. The system could be used to test the effectiveness of making configuration changes, implementing an intrusion detection system, etc. The analysis system requires as input a database of common attacks, broken into atomic steps, specific network configuration and topology information, and an attacker profile. The attack information is "matched" with the network configuration information and an attacker profile to create a superset attack graph. Nodes identify a stage of attack, for example the class of machines the attacker has accessed and the user privilege level he or she has compromised. The arcs in the attack graph represent attacks or stages of attacks. By assigning probabilities of success on the arcs or costs representing level-of-effort for the attacker, various graph algorithms such as shortest-path algorithms can identify the attack paths with the highest probability of success.},
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journal = {Proceedings New Security Paradigms Workshop},
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author = {Phillips, Cynthia and Swiler, Laura Painton},
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note = {doi: 10.1145/310889.310919},
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year = {1998},
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keywords = {Attack graph, Computer security, Network vulnerability},
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pages = {71--79},
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file = {310889.310919:/home/noah/Zotero/storage/JMW5DI72/310889.310919.pdf:application/pdf},
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}
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@article{ou_scalable_2006,
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title = {A {Scalable} {Approach} to {Attack} {Graph} {Generation}},
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issn = {1595935185},
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author = {Ou, Xinming and Boyer, Wayne F and Mcqueen, Miles A},
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year = {2006},
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journal = {CCS '06: Proceedings of the 13th ACM conference on Computer and communications security},
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keywords = {attack graphs, enterprise network security, logic-programming},
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pages = {336--345},
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file = {1180405.1180446:/home/noah/Zotero/storage/TJKHVC4R/1180405.1180446.pdf:application/pdf},
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}
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@misc{j_hale_compliance_nodate,
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title = {Compliance {Method} for a {Cyber}-{Physical} {System}},
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author = {{J. Hale} and Hawrylak, P. and Papa, M.},
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note = {U.S. Patent Number 9,471,789, Oct. 18, 2016.},
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number = {9471789},
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file = {Complaince_Graph_US_Patent_9471789:/home/noah/Zotero/storage/55BZN4U7/Complaince_Graph_US_Patent_9471789.pdf:application/pdf},
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}
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@inproceedings{baloyi_guidelines_2019,
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address = {Skukuza South Africa},
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title = {Guidelines for {Data} {Privacy} {Compliance}: {A} {Focus} on {Cyberphysical} {Systems} and {Internet} of {Things}},
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doi = {10.1145/3351108.3351143},
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booktitle = {{SAICSIT} '19: {Proceedings} of the {South} {African} {Institute} of {Computer} {Scientists} and {Information} {Technologists} 2019},
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publisher = {Association for Computing Machinery},
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author = {Baloyi, Ntsako and Kotzé, Paula},
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year = {2019},
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}
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@article{allman_complying_2006,
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title = {Complying with {Compliance}: {Blowing} it off is not an option.},
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volume = {4},
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number = {7},
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journal = {ACM Queue},
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author = {Allman, Eric},
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year = {2006},
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}
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@article{sheyner_automated_2002,
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title = {Automated {Generation} and {Analysis} of {Attack} {Graphs}},
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issn = {9781787284395},
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journal = {Proceeding of 2002 IEEE Symposium on Security and Privacy},
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author = {Sheyner, O. and Haines, J. and Jha, S. and Lippmann, R.. and Wing, J.},
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year = {2002},
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pages = {254--265},
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file = {sheyner-wing02:/home/noah/Zotero/storage/BV6NHT6L/sheyner-wing02.pdf:application/pdf},
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}
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@article{zhang_boosting_2017,
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title = {Boosting the performance of {FPGA}-based graph processor using hybrid memory cube: {A} case for breadth first search},
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issn = {9781450343541},
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doi = {10.1145/3020078.3021737},
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abstract = {Large graph processing has gained great attention in recent years due to its broad applicability from machine learning to social science. Large real-world graphs, however, are inherently difficult to process efficiently, not only due to their large memory footprint, but also that most graph algorithms entail memory access patterns with poor locality and a low compute-to-memory access ratio. In this work, we leverage the exceptional random access performance of emerging Hybrid Memory Cube (HMC) technology that stacks multiple DRAM dies on top of a logic layer, combined with the flexibility and efficiency of FPGA to address these challenges. To our best knowledge, this is the first work that implements a graph processing system on a FPGA-HMC platform based on software/hardware co-design and co-optimization. We first present the modifications of algorithm and a platform-aware graph processing architecture to perform level-synchronized breadth first search (BFS) on FPGA-HMC platform. To gain better insights into the potential bottlenecks of proposed implementation, we develop an analytical performance model to quantitatively evaluate the HMC access latency and corresponding BFS performance. Based on the analysis, we propose a two-level bitmap scheme to further reduce memory access and perform optimization on key design parameters (e.g. memory access granularity). Finally, we evaluate the performance of our BFS implementation using the AC-510 development kit from Micron. We achieved 166 million edges traversed per second (MTEPS) using GRAPH500 benchmark on a random graph with a scale of 25 and an edge factor of 16, which significantly outperforms CPU and other FPGA-based large graph processors.},
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journal = {FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays},
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author = {Zhang, Jialiang and Khoram, Soroosh and Li, Jing},
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year = {2017},
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pages = {207--216},
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file = {Boosting the Performance of FPGA-based Graph Processor using Hybrdi Memory Cube:/home/noah/Zotero/storage/CDKPUXYF/Boosting the Performance of FPGA-based Graph Processor using Hybrdi Memory Cube.pdf:application/pdf},
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}
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@inproceedings{Monotonicity,
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author = {Ammann, Paul and Wijesekera, Duminda and Kaushik, Saket},
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title = {Scalable, Graph-Based Network Vulnerability Analysis},
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year = {2002},
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isbn = {1581136129},
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publisher = {Association for Computing Machinery},
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address = {New York, NY, USA},
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url = {https://doi.org/10.1145/586110.586140},
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doi = {10.1145/586110.586140},
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abstract = {Even well administered networks are vulnerable to attack. Recent work in network security has focused on the fact that combinations of exploits are the typical means by which an attacker breaks into a network. Researchers have proposed a variety of graph-based algorithms to generate attack trees (or graphs). Either structure represents all possible sequences of exploits, where any given exploit can take advantage of the penetration achieved by prior exploits in its chain, and the final exploit in the chain achieves the attacker's goal. The most recent approach in this line of work uses a modified version of the model checker NuSMV as a powerful inference engine for chaining together network exploits, compactly representing attack graphs, and identifying minimal sets of exploits. However, it is also well known that model checkers suffer from scalability problems, and there is good reason to doubt whether a model checker can handle directly a realistic set of exploits for even a modest-sized network. In this paper, we revisit the idea of attack graphs themselves, and argue that they represent more information explicitly than is necessary for the analyst. Instead, we propose a more compact and scalable representation. Although we show that it is possible to produce attack trees from our representation, we argue that more useful information can be produced, for larger networks, while bypassing the attack tree step. Our approach relies on an explicit assumption of monotonicity, which, in essence, states that the precondition of a given exploit is never invalidated by the successful application of another exploit. In other words, the attacker never needs to backtrack. The assumption reduces the complexity of the analysis problem from exponential to polynomial, thereby bringing even very large networks within reach of analysis},
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booktitle = {Proceedings of the 9th ACM Conference on Computer and Communications Security},
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pages = {217–224},
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numpages = {8},
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keywords = {network security, scalability, model checking, monotonic analysis, exploit, vulnerability},
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location = {Washington, DC, USA},
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series = {CCS '02}
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}
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@inbook{TVA,
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author = {Jajodia, Sushil and Noel, Steven},
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year = {2010},
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month = {09},
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pages = {139-154},
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title = {Topological Vulnerability Analysis},
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volume = {46},
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isbn = {978-1-4419-0139-2},
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journal = {Cyber Situational Awareness, Advances in Information Security, Volume 46. ISBN 978-1-4419-0139-2. Springer-Verlag US, 2010, p. 139},
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doi = {10.1007/978-1-4419-0140-8_7}
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}
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@phdthesis{louthan_hybrid_2011,
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title = {Hybrid {Attack} {Graphs} for {Modeling} {Cyber}-{Physical} {Systems}},
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author = {Louthan, G},
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school = {The {University} of {Tulsa}},
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year = {2011},
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keywords = {icle},
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file = {louthan_thesis:/home/noah/Zotero/storage/5SBCLYA3/louthan_thesis.pdf:application/pdf},
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}
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@phdthesis{cook_rage_2018,
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title = {{RAGE}: {The} {Rage} {Attack} {Graph} {Engine}},
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author = {Cook, Kyle},
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school = {The {University} of {Tulsa}},
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year = {2018},
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file = {Kyle Cook Thesis:/home/noah/Zotero/storage/2SR28HM2/Kyle Cook Thesis.pdf:application/pdf},
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}
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@phdthesis{nichols_2018,
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title = {{Hybrid} {Attack} {Graphs} for {Use} with a {Simulation} of a {Cyber-Physical} {System}},
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author = {Nichols, Will M.},
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school = {The {University} of {Tulsa}},
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year = {2018},
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file = {Will_Nichols_Thesis_FINAL_VER:/home/noah/Zotero/storage/8AXSZXJN/Will_Nichols_Thesis_FINAL_VER.pdf:application/pdf},
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} |