Related Works
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@phdthesis{noauthor_notitle_nodate,
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}
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@INPROCEEDINGS{9150145,
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author={Li, Ming and Hawrylak, Peter J. and Hale, John},
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booktitle={2020 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},
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title={Implementing an Attack Graph Generator in CUDA},
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year={2020},
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volume={},
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number={},
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pages={730-738},
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doi={10.1109/IPDPSW50202.2020.00128}}
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@ARTICLE{7087377, author={Kaynar, Kerem and Sivrikaya, Fikret}, journal={IEEE Transactions on Dependable and Secure Computing}, title={Distributed Attack Graph Generation}, year={2016}, volume={13}, number={5}, pages={519-532}, doi={10.1109/TDSC.2015.2423682}}
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@ -56,7 +56,7 @@ The objectives of this thesis are:
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\end{enumerate}
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\item{Implement solutions to reduce state space explosion while remaining exhaustive and capturing all necessary information}
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\item{Extend RAGE to function for heterogeneous distributed computing environments}
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\item{Utilize RAGE for compliance graph generation}
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\item{Extend and utilize RAGE for compliance graph generation}
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\end{itemize}
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36
Chapter2.aux
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Chapter2.aux
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\citation{berry_graph_2007}
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40
Chapter2.tex
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Chapter2.tex
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\TUchapter{RELATED WORKS}
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Many authors and researchers have developed or extended attack graphs since their beginning
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as attack trees. This Chapter reviews a few of their efforts as they relate to this work.
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as attack trees. This Chapter reviews a few of their efforts as they relate to this work and to graph generation.
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\TUsection{Introduction to Graph Generation}
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Graph generation as a broad topic has many challenges that prevent full actualization of computation seen from a theoretical standpoint.
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In actuality, graph generation often achieves only a very low percentage of its expected performance \cite{berry_graph_2007}. A few reasons
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for this occurence lies in the underlying mechanisms of graph generation. The generation is predominantly memory based (as opposed to based on processor speed),
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where performance is tied to memory access time, the complexity of data dependency, and coarseness of parallelism \cite{berry_graph_2007}, \cite{zhang_boosting_2017},
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\cite{ainsworth_graph_2016}. The graph generation process is typically quite poor, resulting in lower performance results. Graphs consume large amounts of memory through their
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nodes and edges, graph data structures suffer from poor cache locality, and memory latency from the processor-memory gap all slow the generation process dramatically
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\cite{berry_graph_2007}, \cite{ainsworth_graph_2016}. Section \ref{sec:gen_improv} discusses a few works that can be used to improve the graph generation process, and Section
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\ref{sec:related_works} discusses a few works specific to attack graph generation improvements.
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\TUsection{Improvements to Attack Graph Generation} \label{sec:related_works}
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\TUsection{Graph Generation Improvements} \label{sec:gen_improv}
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For architectural and hardware techinques for generation improvement, the authors of \cite{ainsworth_graph_2016} discuss the high cache miss rate, and how general prefetching
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leads does not increase the prediction rate due to non-sequenial graph structures and data-dependent access patterns. However, the authors continue to discuss that the generation
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algorithm is known in advance, so explicit tuning of the hardware prefetcher to follow the traversal order pattern can lead to better performance. The authors were able to achieve
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over 2x performance improvement of a breadth-first search approach with this method. Another hardware approach is to make use of accelerators. The authors of \cite{yao_efficient_2018}
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present an approach for minimizing the slowdown caused by the underlying graph atomic functions. By using the atomic function patterns, the authors utilized pipeline stages where vertex
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updates can be processed in parallel dynamically. Other works, such as those by the authors of \cite{zhang_boosting_2017} and \cite{dai_fpgp_2016}, leverage field-programmable gate arrays
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(FPGAs) for graph generation in the HPC space through various means. This includes reducing memory strain, storing repeatedly accessed lists, storing results, or other storage through the
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on-chip block RAM, or even levering Hybrid Memory Cubes for optimizing parallel access.
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\TUsection{Attack Dependency Graphs}
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From a data structure standpoint, the authors of \cite{arifuzzaman_fast_2015} describe the infeasibility of adjacency matrices in large-scale graphs, and this work and other works such as those
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by the authors of \cite{yu_construction_2018} and \cite{liakos_memory-optimized_2016} discuss the appeal of distibuting a graph representation among systems. The author of
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\cite{liakos_memory-optimized_2016} disuss the usage of distributed adjacency lists for assinging vertices to workers. The authors of \cite{liakos_memory-optimized_2016} and
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\cite{balaji_graph_2016} present other techniques for minimizing communication costs by achieving high compression ratios while maintaining a low compression cost. The Boost Graph Library
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and the Parallel Boost Graph Library both provide appealing features for working with graps, with the latter library notably having interoperability with MPI, Graphviz, and METIS
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\cite{noauthor_overview_nodate}, \cite {noauthor_boost_nodate}.
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\TUsection{Compliance Graphs}
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\TUsection{Improvements Specific to Attack Graph Generation} \label{sec:related_works}
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As a means of improving scalability of attack graphs, the authors of \cite{ou_scalable_2006} present a new representation scheme. Traditional attack graphs encode the entire network at each state,
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but this representation uses logical statements to represent a portion of the network at each node. This is called a logical attack graph. This approach led to the reduction of the generation process
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to quadratic time and reduced the number of nodes in the resulting graph to $\mathcal{O}({n}^2)$. However, this approach does require more analysis for identifying attack vectors. Another approach
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presented by the authors of \cite{cook_scalable_2016} represent a description of systems and their qualities and topologies as a state, with a queue of unexplored states. This work was continued by the
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authors of \cite{li_concurrency_2019} by implementing a hash table among other features. Each of these works demonstrate an improvement in scalability through refining the desirable information.
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Another approach for generation improvement is through parallelization. The authors of \cite{li_concurrency_2019} leverage OpenMP to parallelize the exploration of a FIFO queue. This parallelization also
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includes the utilization of OpenMP's dynamic scheduling. In this approach, each thread receives a state to explore, where a critical section is employed to handle the atomic functions of merging new state
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information while avoiding collisions, race conditions, or stale data usage. The authors measured a 10x speedup over the serial algorithm. The authors of \cite{9150145} present a parallel generation
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approach using CUDA, where speedup is obtained through a large number of CUDA cores. For a distributed approach, the authors of \cite{7087377} present a technique for utilizing reachability hyper-graph partitioning
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and a virtual shared memory abstraction to prevent duplicate work by multiple nodes. This work had promising results in terms of limiting the state-space explosion and speedup as the number of network hosts increases.
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
\@input{Appendices.aux}
|
||||
\gdef \@abspage@last{36}
|
||||
\gdef \@abspage@last{39}
|
||||
|
||||
@ -1,5 +1,11 @@
|
||||
\begin{thebibliography}{10}
|
||||
|
||||
\bibitem{noauthor_boost_nodate}
|
||||
The {Boost} {Graph} {Library} - 1.75.0.
|
||||
|
||||
\bibitem{noauthor_overview_nodate}
|
||||
An {Overview} of the {Parallel} {Boost} {Graph} {Library} - 1.75.0.
|
||||
|
||||
\bibitem{ainsworth_graph_2016}
|
||||
Sam Ainsworth and Timothy~M. Jones.
|
||||
\newblock Graph prefetching using data structure knowledge.
|
||||
@ -11,6 +17,19 @@ Eric Allman.
|
||||
\newblock Complying with {Compliance}: {Blowing} it off is not an option.
|
||||
\newblock {\em ACM Queue}, 4(7), 2006.
|
||||
|
||||
\bibitem{arifuzzaman_fast_2015}
|
||||
Shaikh Arifuzzaman and Maleq Khan.
|
||||
\newblock Fast parallel conversion of edge list to adjacency list for
|
||||
large-scale graphs.
|
||||
\newblock In {\em {HPC} '15: {Proceedings} of the {Symposium} on {High}
|
||||
{Performance} {Computing}}, pages 17--24, April 2015.
|
||||
|
||||
\bibitem{balaji_graph_2016}
|
||||
Janani Balaji and Rajshekhar Sunderraman.
|
||||
\newblock Graph {Topology} {Abstraction} for {Distributed} {Path} {Queries}.
|
||||
\newblock In {\em {HPGP} '16: {Proceedings} of the {ACM} {Workshop} on {High}
|
||||
{Performance} {Graph} {Processing}}, pages 27--34, May 2016.
|
||||
|
||||
\bibitem{baloyi_guidelines_2019}
|
||||
Ntsako Baloyi and Paula Kotzé.
|
||||
\newblock Guidelines for {Data} {Privacy} {Compliance}: {A} {Focus} on
|
||||
@ -29,6 +48,12 @@ Kyle Cook.
|
||||
\newblock {\em {RAGE}: {The} {Rage} {Attack} {Graph} {Engine}}.
|
||||
\newblock PhD thesis, 2018.
|
||||
|
||||
\bibitem{cook_scalable_2016}
|
||||
Kyle Cook, Thomas Shaw, John Hale, and Peter Hawrylak.
|
||||
\newblock Scalable attack graph generation.
|
||||
\newblock {\em Proceedings of the 11th Annual Cyber and Information Security
|
||||
Research Conference, CISRC 2016}, 2016.
|
||||
|
||||
\bibitem{CVE-2019-10747}
|
||||
{set-value is vulnerable to Prototype Pollution in versions lower than 3.0.1.
|
||||
The function mixin-deep could be tricked into adding or modifying properties
|
||||
@ -36,10 +61,23 @@ Kyle Cook.
|
||||
payloads.}
|
||||
\newblock National Vulnerability Database, August 2019.
|
||||
|
||||
\bibitem{dai_fpgp_2016}
|
||||
Guohao Dai, Yuze Chi, Yu~Wang, and Huazhong Yang.
|
||||
\newblock {FPGP}: {Graph} processing framework on {FPGA}: {A} case study of
|
||||
breadth-first search.
|
||||
\newblock {\em FPGA 2016 - Proceedings of the 2016 ACM/SIGDA International
|
||||
Symposium on Field-Programmable Gate Arrays}, pages 105--110, 2016.
|
||||
|
||||
\bibitem{j_hale_compliance_nodate}
|
||||
{J. Hale}, P.~Hawrylak, and M.~Papa.
|
||||
\newblock Compliance {Method} for a {Cyber}-{Physical} {System}.
|
||||
|
||||
\bibitem{7087377}
|
||||
Kerem Kaynar and Fikret Sivrikaya.
|
||||
\newblock Distributed attack graph generation.
|
||||
\newblock {\em IEEE Transactions on Dependable and Secure Computing},
|
||||
13(5):519--532, 2016.
|
||||
|
||||
\bibitem{li_combining_2019}
|
||||
Ming Li, Peter Hawrylak, and John Hale.
|
||||
\newblock Combining {OpenCL} and {MPI} to support heterogeneous computing on a
|
||||
@ -52,6 +90,20 @@ Ming Li, Peter Hawrylak, and John Hale.
|
||||
\newblock {\em Proceedings - 2019 2nd International Conference on Data
|
||||
Intelligence and Security, ICDIS 2019}, pages 174--179, 2019.
|
||||
|
||||
\bibitem{9150145}
|
||||
Ming Li, Peter~J. Hawrylak, and John Hale.
|
||||
\newblock Implementing an attack graph generator in cuda.
|
||||
\newblock In {\em 2020 IEEE International Parallel and Distributed Processing
|
||||
Symposium Workshops (IPDPSW)}, pages 730--738, 2020.
|
||||
|
||||
\bibitem{liakos_memory-optimized_2016}
|
||||
Panagiotis Liakos, Katia Papakonstantinopoulou, and Alex Delis.
|
||||
\newblock Memory-{Optimized} {Distributed} {Graph} {Processing} through {Novel}
|
||||
{Compression} {Techniques}.
|
||||
\newblock In {\em {CIKM} '16: {Proceedings} of the 25th {ACM} {International}
|
||||
{Conference} on {Information} and {Knowledge} {Management}}, pages
|
||||
2317--2322, October 2016.
|
||||
|
||||
\bibitem{ou_scalable_2006}
|
||||
Xinming Ou, Wayne~F Boyer, and Miles~A Mcqueen.
|
||||
\newblock A {Scalable} {Approach} to {Attack} {Graph} {Generation}.
|
||||
@ -74,6 +126,22 @@ O.~Sheyner, J.~Haines, S.~Jha, R.. Lippmann, and J.~Wing.
|
||||
\newblock {\em Proceeding of 2002 IEEE Symposium on Security and Privacy},
|
||||
pages 254--265, 2002.
|
||||
|
||||
\bibitem{yao_efficient_2018}
|
||||
Pengcheng Yao, Long Zheng, Xiaofei Liao, Hai Jin, and Bingsheng He.
|
||||
\newblock An efficient graph accelerator with parallel data conflict
|
||||
management.
|
||||
\newblock {\em Parallel Architectures and Compilation Techniques - Conference
|
||||
Proceedings, PACT}, 2018.
|
||||
|
||||
\bibitem{yu_construction_2018}
|
||||
Xinjie Yu, Wentao Chen, Jiajia Miao, Jian Chen, Handong Mao, Qiong Luo, and Lin
|
||||
Gu.
|
||||
\newblock The {Construction} of {Large} {Graph} {Data} {Structures} in a
|
||||
{Scalable} {Distributed} {Message} {System}.
|
||||
\newblock In {\em {HPCCT} 2018: {Proceedings} of the 2018 2nd {High}
|
||||
{Performance} {Computing} and {Cluster} {Technologies} {Conference}}, pages
|
||||
6--10, June 2018.
|
||||
|
||||
\bibitem{zhang_boosting_2017}
|
||||
Jialiang Zhang, Soroosh Khoram, and Jing Li.
|
||||
\newblock Boosting the performance of {FPGA}-based graph processor using hybrid
|
||||
|
||||
@ -13,47 +13,49 @@ A level-1 auxiliary file: Appendices.aux
|
||||
Database file #1: Bibliography.bib
|
||||
Warning--entry type for "j_hale_compliance_nodate" isn't style-file defined
|
||||
--line 272 of file Bibliography.bib
|
||||
Warning--to sort, need author or key in noauthor_overview_nodate
|
||||
Warning--to sort, need author or key in noauthor_boost_nodate
|
||||
Warning--empty school in cook_rage_2018
|
||||
Warning--empty journal in ou_scalable_2006
|
||||
You've used 14 entries,
|
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|
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2118 wiz_defined-function locations,
|
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577 strings with 6718 characters,
|
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
628 strings with 9040 characters,
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
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|
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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