Adding Related Works
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@ -1,9 +1,75 @@
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\begin{thebibliography}{1}
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\begin{thebibliography}{10}
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\bibitem{pacheco_introduction_2011}
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P.~Pacheco, {\em An {Introduction} to {Parallel} {Programming}}.
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\newblock Morgan Kaufmann, print~ed., 2011.
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\bibitem{ainsworth_graph_2016}
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S.~Ainsworth and T.~M. Jones, ``Graph prefetching using data structure
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knowledge,'' {\em Proceedings of the International Conference on
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Supercomputing}, vol.~01-03-June, 2016.
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\bibitem{yao_efficient_2018}
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P.~Yao, L.~Zheng, X.~Liao, H.~Jin, and B.~He, ``An efficient graph accelerator
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with parallel data conflict management,'' {\em Parallel Architectures and
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Compilation Techniques - Conference Proceedings, PACT}, 2018.
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\bibitem{zhang_boosting_2017}
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J.~Zhang, S.~Khoram, and J.~Li, ``Boosting the performance of {FPGA}-based
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graph processor using hybrid memory cube: {A} case for breadth first
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search,'' {\em FPGA 2017 - Proceedings of the 2017 ACM/SIGDA International
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Symposium on Field-Programmable Gate Arrays}, pp.~207--216, 2017.
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\bibitem{dai_fpgp_2016}
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G.~Dai, Y.~Chi, Y.~Wang, and H.~Yang, ``{FPGP}: {Graph} processing framework on
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{FPGA}: {A} case study of breadth-first search,'' {\em FPGA 2016 -
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Proceedings of the 2016 ACM/SIGDA International Symposium on
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Field-Programmable Gate Arrays}, pp.~105--110, 2016.
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\bibitem{arifuzzaman_fast_2015}
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S.~Arifuzzaman and M.~Khan, ``Fast parallel conversion of edge list to
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adjacency list for large-scale graphs,'' in {\em {HPC} '15: {Proceedings} of
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the {Symposium} on {High} {Performance} {Computing}}, pp.~17--24, Apr. 2015.
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\bibitem{yu_construction_2018}
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X.~Yu, W.~Chen, J.~Miao, J.~Chen, H.~Mao, Q.~Luo, and L.~Gu, ``The
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{Construction} of {Large} {Graph} {Data} {Structures} in a {Scalable}
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{Distributed} {Message} {System},'' in {\em {HPCCT} 2018: {Proceedings} of
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the 2018 2nd {High} {Performance} {Computing} and {Cluster} {Technologies}
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{Conference}}, pp.~6--10, June 2018.
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\bibitem{liakos_memory-optimized_2016}
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P.~Liakos, K.~Papakonstantinopoulou, and A.~Delis, ``Memory-{Optimized}
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{Distributed} {Graph} {Processing} through {Novel} {Compression}
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{Techniques},'' in {\em {CIKM} '16: {Proceedings} of the 25th {ACM}
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{International} {Conference} on {Information} and {Knowledge} {Management}},
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pp.~2317--2322, Oct. 2016.
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\bibitem{balaji_graph_2016}
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J.~Balaji and R.~Sunderraman, ``Graph {Topology} {Abstraction} for
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{Distributed} {Path} {Queries},'' in {\em {HPGP} '16: {Proceedings} of the
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{ACM} {Workshop} on {High} {Performance} {Graph} {Processing}}, pp.~27--34,
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May 2016.
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\bibitem{noauthor_overview_nodate}
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``An {Overview} of the {Parallel} {Boost} {Graph} {Library} - 1.75.0,'' 2009.
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\bibitem{noauthor_boost_nodate}
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J.~Siek, L.-Q. Lee, and A.~Lumsdaine, ``The {Boost} {Graph} {Library}, vers.
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1.75.0.''
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\newblock
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{https://www.boost.org/doc/libs/1$\_$75$\_$0/libs/graph/doc/index.html}.
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\bibitem{ou_scalable_2006}
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X.~Ou, W.~F. Boyer, and M.~A. Mcqueen, ``A {Scalable} {Approach} to {Attack}
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{Graph} {Generation},'' {\em CCS '06: Proceedings of the 13th ACM conference
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on Computer and communications security}, pp.~336--345, 2006.
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\bibitem{cook_scalable_2016}
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K.~Cook, T.~Shaw, J.~Hale, and P.~Hawrylak, ``Scalable attack graph
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generation,'' {\em Proceedings of the 11th Annual Cyber and Information
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Security Research Conference, CISRC 2016}, 2016.
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\bibitem{li_concurrency_2019}
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M.~Li, P.~Hawrylak, and J.~Hale, ``Concurrency {Strategies} for {Attack}
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{Graph} {Generation},'' {\em Proceedings - 2019 2nd International Conference
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@ -55,7 +55,23 @@ Attack Graph; Compliance Graph; MPI; High-Performance Computing; Cybersecurity;
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This work attempts to further those efforts and extend RAGE to function on distributed computing environments to take advantage of the increased computing power using message-passing. As mentioned by the author of \cite{pacheco_introduction_2011}, MPI is the most widely used message-passing API, and this work intended to utilize an API that was not only familiar and accessible, but versatile and powerful for parallelizing RAGE for distributed computing platforms. This work discusses a task parallelism approach for the generation process, and uses OpenMPI for the MPI implementation.
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\section{Related Works}
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Previous works for graph generation, and specifically for attack graph generation, have seen promising results as discussed in Sections \ref{sec:gen_improv} and \ref{sec:related_works}.
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For architectural and hardware techniques for general graph generation improvement, the authors of \cite{ainsworth_graph_2016} discuss the high cache miss rate, and how general prefetching
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does not increase the prediction rate due to nonsequential graph structures and data-dependent access patterns. However, the authors continue to discuss that generation algorithms are known in advance, so explicit tuning of the hardware prefetcher to follow the traversal order pattern can lead to better performance. The authors were able to achieve over 2x performance improvement of a breadth-first search approach with this method.
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Another hardware approach is to make use of accelerators. The authors of \cite{yao_efficient_2018} present an approach for minimizing the slowdown caused by the underlying graph atomic functions. By using the atomic function patterns, the authors utilized pipeline stages where vertex updates can be processed in parallel dynamically.
|
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Other works, such as those by the authors of \cite{zhang_boosting_2017} and \cite{dai_fpgp_2016}, leverage field-programmable gate arrays (FPGAs) for graph generation in the HPC space through various means. This includes reducing memory strain, storing repeatedly accessed lists, storing results, or other storage through the on-chip block RAM, or even leveraging Hybrid Memory Cubes for optimizing parallel access.
|
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From a data structure standpoint, the authors of \cite{arifuzzaman_fast_2015} describe the infeasibility of adjacency matrices in large-scale graphs, and this work and other works such as those by the authors of \cite{yu_construction_2018} and \cite{liakos_memory-optimized_2016} discuss the appeal of distributing a graph representation across systems.
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The author of \cite{liakos_memory-optimized_2016} discusses the usage of distributed adjacency lists for assigning vertices to workers.
|
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The authors of \cite{liakos_memory-optimized_2016} and \cite{balaji_graph_2016} present other techniques for minimizing communication costs by achieving high compression ratios while maintaining a low compression cost.
|
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The Boost Graph Library and the Parallel Boost Graph Library both provide appealing features for working with graphs, with the latter library notably having interoperability with MPI, Graphviz, and METIS \cite{noauthor_overview_nodate}, \cite{noauthor_boost_nodate}.
|
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There have also been numerous approaches at generation improvement specific to attack graphs. As a means of improving scalability of attack graphs, the authors of \cite{ou_scalable_2006} present a new representation scheme. Traditional attack graphs encode the entire network at each state, but the representation presented by the authors uses logical statements to represent a portion of the network at each node. This is called a logical attack graph. This approach led to the reduction of the generation process to quadratic time and reduced the number of nodes in the resulting graph to $\mathcal{O}({n}^2)$. However, this approach does require more analysis for identifying attack vectors.
|
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Another approach presented by the authors of \cite{cook_scalable_2016} represents a description of systems and their qualities and topologies as a state, with a queue of unexplored states.
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This work was continued by the authors of \cite{li_concurrency_2019} by implementing a hash table among other features. Each of these works demonstrates an improvement in scalability through refining the desirable information output.
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Another approach for generation improvement is through parallelization. The authors of \cite{li_concurrency_2019} leverage OpenMP to parallelize the exploration of a FIFO queue. This parallelization also includes the utilization of OpenMP's dynamic scheduling. In this approach, each thread receives a state to explore, where a critical section is employed to handle the atomic functions of merging new state information while avoiding collisions, race conditions, or stale data usage. The authors measured a 10x speedup over the serial algorithm.
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The authors of \cite{9150145} present a parallel generation approach using CUDA, where speedup is obtained through a large number of CUDA cores.
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For a distributed approach, the authors of \cite{7087377} present a technique for utilizing reachability hyper-graph partitioning and a virtual shared memory abstraction to prevent duplicate work by multiple nodes. This work had promising results in terms of limiting the state-space explosion and speedup as the number of network hosts increases.
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\section{Necessary Components}
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\subsection{Serialization}
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